  1// From: https://github.com/cnlohr/mini-rv32ima
  2// Author: Charles Lohr (BSD/MIT/CC0 Licence)
  3// Copyright 2022 Charles Lohr, you may use this file or any portions herein under any of the BSD, MIT, or CC0 licenses.
  4
  5#ifndef _MINI_RV32IMAH_H
  6#define _MINI_RV32IMAH_H
  7
  8/**
  9    To use mini-rv32ima.h for the bare minimum, the following:
 10
 11  #define MINI_RV32_RAM_SIZE ram_amt
 12  #define MINIRV32_IMPLEMENTATION
 13
 14  #include "mini-rv32ima.h"
 15
 16  Though, that's not _that_ interesting. You probably want I/O!
 17
 18
 19  Notes:
 20    * There is a dedicated CLNT at 0x10000000.
 21    * There is free MMIO from there to 0x12000000.
 22    * You can put things like a UART, or whatever there.
 23    * Feel free to override any of the functionality with macros.
 24*/
 25
 26#ifndef MINIRV32WARN
 27  #define MINIRV32WARN( x... );
 28#endif
 29
 30#ifndef MINIRV32_DECORATE
 31  #define MINIRV32_DECORATE static
 32#endif
 33
 34#ifndef MINIRV32_RAM_IMAGE_OFFSET
 35  #define MINIRV32_RAM_IMAGE_OFFSET  0x80000000
 36#endif
 37
 38#ifndef MINIRV32_POSTEXEC
 39  #define MINIRV32_POSTEXEC(...);
 40#endif
 41
 42#ifndef MINIRV32_HANDLE_MEM_STORE_CONTROL
 43  #define MINIRV32_HANDLE_MEM_STORE_CONTROL(...);
 44#endif
 45
 46#ifndef MINIRV32_HANDLE_MEM_LOAD_CONTROL
 47  #define MINIRV32_HANDLE_MEM_LOAD_CONTROL(...);
 48#endif
 49
 50#ifndef MINIRV32_OTHERCSR_WRITE
 51  #define MINIRV32_OTHERCSR_WRITE(...);
 52#endif
 53
 54#ifndef MINIRV32_OTHERCSR_READ
 55  #define MINIRV32_OTHERCSR_READ(...);
 56#endif
 57
 58#ifndef MINIRV32_CUSTOM_MEMORY_BUS
 59  #define MINIRV32_STORE4( ofs, val ) *(uint32_t*)(image + ofs) = val
 60  #define MINIRV32_STORE2( ofs, val ) *(uint16_t*)(image + ofs) = val
 61  #define MINIRV32_STORE1( ofs, val ) *(uint8_t*)(image + ofs) = val
 62  #define MINIRV32_LOAD4( ofs ) *(uint32_t*)(image + ofs)
 63  #define MINIRV32_LOAD2( ofs ) *(uint16_t*)(image + ofs)
 64  #define MINIRV32_LOAD1( ofs ) *(uint8_t*)(image + ofs)
 65#endif
 66
 67// As a note: We quouple-ify these, because in HLSL, we will be operating with
 68// uint4's.  We are going to uint4 data to/from system RAM.
 69//
 70// We're going to try to keep the full processor state to 12 x uint4.
 71struct MiniRV32IMAState
 72{
 73  uint32_t regs[32];
 74
 75  uint32_t pc;
 76  uint32_t mstatus;
 77  uint32_t cyclel;
 78  uint32_t cycleh;
 79
 80  uint32_t timerl;
 81  uint32_t timerh;
 82  uint32_t timermatchl;
 83  uint32_t timermatchh;
 84
 85  uint32_t mscratch;
 86  uint32_t mtvec;
 87  uint32_t mie;
 88  uint32_t mip;
 89
 90  uint32_t mepc;
 91  uint32_t mtval;
 92  uint32_t mcause;
 93
 94  // Note: only a few bits are used.  (Machine = 3, User = 0)
 95  // Bits 0..1 = privilege.
 96  // Bit 2 = WFI (Wait for interrupt)
 97  // Bit 3+ = Load/Store reservation LSBs.
 98  uint32_t extraflags;
 99};
100
101MINIRV32_DECORATE int32_t MiniRV32IMAStep( struct MiniRV32IMAState * state, uint8_t * image, uint32_t vProcAddress, uint32_t elapsedUs, int count );
102
103#ifdef MINIRV32_IMPLEMENTATION
104
105#define CSR( x ) state->x
106#define SETCSR( x, val ) { state->x = val; }
107#define REG( x ) state->regs[x]
108#define REGSET( x, val ) { state->regs[x] = val; }
109
110MINIRV32_DECORATE int32_t MiniRV32IMAStep( struct MiniRV32IMAState * state, uint8_t * image, uint32_t vProcAddress, uint32_t elapsedUs, int count )
111{
112  uint32_t new_timer = CSR( timerl ) + elapsedUs;
113  if( new_timer < CSR( timerl ) ) CSR( timerh )++;
114  CSR( timerl ) = new_timer;
115
116  // Handle Timer interrupt.
117  if( ( CSR( timerh ) > CSR( timermatchh ) || ( CSR( timerh ) == CSR( timermatchh ) && CSR( timerl ) > CSR( timermatchl ) ) ) && ( CSR( timermatchh ) || CSR( timermatchl ) ) )
118  {
119    CSR( extraflags ) &= ~4; // Clear WFI
120    CSR( mip ) |= 1<<7; //MTIP of MIP // https://stackoverflow.com/a/61916199/2926815  Fire interrupt.
121  }
122  else
123    CSR( mip ) &= ~(1<<7);
124
125  // If WFI, don't run processor.
126  if( CSR( extraflags ) & 4 )
127    return 1;
128
129  uint32_t trap = 0;
130  uint32_t rval = 0;
131  uint32_t pc = CSR( pc );
132  uint32_t cycle = CSR( cyclel );
133
134  if( ( CSR( mip ) & (1<<7) ) && ( CSR( mie ) & (1<<7) /*mtie*/ ) && ( CSR( mstatus ) & 0x8 /*mie*/) )
135  {
136    // Timer interrupt.
137    trap = 0x80000007;
138    pc -= 4;
139  }
140  else // No timer interrupt?  Execute a bunch of instructions.
141  for( int icount = 0; icount < count; icount++ )
142  {
143    uint32_t ir = 0;
144    rval = 0;
145    cycle++;
146    uint32_t ofs_pc = pc - MINIRV32_RAM_IMAGE_OFFSET;
147
148    if( ofs_pc  >= MINI_RV32_RAM_SIZE )
149    {
150      trap = 1 + 1;  // Handle access violation on instruction read.
151      break;
152    }
153    else if( ofs_pc & 3 )
154    {
155      trap = 1 + 0;  //Handle PC-misaligned access
156      break;
157    }
158    else
159    {
160      ir = MINIRV32_LOAD4( ofs_pc );
161      uint32_t rdid = (ir >> 7) & 0x1f;
162
163      switch( ir & 0x7f )
164      {
165        case 0b0110111: // LUI
166          rval = ( ir & 0xfffff000 );
167          break;
168        case 0b0010111: // AUIPC
169          rval = pc + ( ir & 0xfffff000 );
170          break;
171        case 0b1101111: // JAL
172        {
173          int32_t reladdy = ((ir & 0x80000000)>>11) | ((ir & 0x7fe00000)>>20) | ((ir & 0x00100000)>>9) | ((ir&0x000ff000));
174          if( reladdy & 0x00100000 ) reladdy |= 0xffe00000; // Sign extension.
175          rval = pc + 4;
176          pc = pc + reladdy - 4;
177          break;
178        }
179        case 0b1100111: // JALR
180        {
181          uint32_t imm = ir >> 20;
182          int32_t imm_se = imm | (( imm & 0x800 )?0xfffff000:0);
183          rval = pc + 4;
184          pc = ( (REG( (ir >> 15) & 0x1f ) + imm_se) & ~1) - 4;
185          break;
186        }
187        case 0b1100011: // Branch
188        {
189          uint32_t immm4 = ((ir & 0xf00)>>7) | ((ir & 0x7e000000)>>20) | ((ir & 0x80) << 4) | ((ir >> 31)<<12);
190          if( immm4 & 0x1000 ) immm4 |= 0xffffe000;
191          int32_t rs1 = REG((ir >> 15) & 0x1f);
192          int32_t rs2 = REG((ir >> 20) & 0x1f);
193          immm4 = pc + immm4 - 4;
194          rdid = 0;
195          switch( ( ir >> 12 ) & 0x7 )
196          {
197            // BEQ, BNE, BLT, BGE, BLTU, BGEU
198            case 0b000: if( rs1 == rs2 ) pc = immm4; break;
199            case 0b001: if( rs1 != rs2 ) pc = immm4; break;
200            case 0b100: if( rs1 < rs2 ) pc = immm4; break;
201            case 0b101: if( rs1 >= rs2 ) pc = immm4; break; //BGE
202            case 0b110: if( (uint32_t)rs1 < (uint32_t)rs2 ) pc = immm4; break;   //BLTU
203            case 0b111: if( (uint32_t)rs1 >= (uint32_t)rs2 ) pc = immm4; break;  //BGEU
204            default: trap = (2+1);
205          }
206          break;
207        }
208        case 0b0000011: // Load
209        {
210          uint32_t rs1 = REG((ir >> 15) & 0x1f);
211          uint32_t imm = ir >> 20;
212          int32_t imm_se = imm | (( imm & 0x800 )?0xfffff000:0);
213          uint32_t rsval = rs1 + imm_se;
214
215          rsval -= MINIRV32_RAM_IMAGE_OFFSET;
216          if( rsval >= MINI_RV32_RAM_SIZE-3 )
217          {
218            rsval += MINIRV32_RAM_IMAGE_OFFSET;
219            if( rsval >= 0x10000000 && rsval < 0x12000000 )  // UART, CLNT
220            {
221              if( rsval == 0x1100bffc ) // https://chromitem-soc.readthedocs.io/en/latest/clint.html
222                rval = CSR( timerh );
223              else if( rsval == 0x1100bff8 )
224                rval = CSR( timerl );
225              else
226                MINIRV32_HANDLE_MEM_LOAD_CONTROL( rsval, rval );
227            }
228            else
229            {
230              trap = (5+1);
231              rval = rsval;
232            }
233          }
234          else
235          {
236            switch( ( ir >> 12 ) & 0x7 )
237            {
238              //LB, LH, LW, LBU, LHU
239              case 0b000: rval = (int8_t)MINIRV32_LOAD1( rsval ); break;
240              case 0b001: rval = (int16_t)MINIRV32_LOAD2( rsval ); break;
241              case 0b010: rval = MINIRV32_LOAD4( rsval ); break;
242              case 0b100: rval = MINIRV32_LOAD1( rsval ); break;
243              case 0b101: rval = MINIRV32_LOAD2( rsval ); break;
244              default: trap = (2+1);
245            }
246          }
247          break;
248        }
249        case 0b0100011: // Store
250        {
251          uint32_t rs1 = REG((ir >> 15) & 0x1f);
252          uint32_t rs2 = REG((ir >> 20) & 0x1f);
253          uint32_t addy = ( ( ir >> 7 ) & 0x1f ) | ( ( ir & 0xfe000000 ) >> 20 );
254          if( addy & 0x800 ) addy |= 0xfffff000;
255          addy += rs1 - MINIRV32_RAM_IMAGE_OFFSET;
256          rdid = 0;
257
258          if( addy >= MINI_RV32_RAM_SIZE-3 )
259          {
260            addy += MINIRV32_RAM_IMAGE_OFFSET;
261            if( addy >= 0x10000000 && addy < 0x12000000 )
262            {
263              // Should be stuff like SYSCON, 8250, CLNT
264              if( addy == 0x11004004 ) //CLNT
265                CSR( timermatchh ) = rs2;
266              else if( addy == 0x11004000 ) //CLNT
267                CSR( timermatchl ) = rs2;
268              else if( addy == 0x11100000 ) //SYSCON (reboot, poweroff, etc.)
269              {
270                SETCSR( pc, pc + 4 );
271                return rs2; // NOTE: PC will be PC of Syscon.
272              }
273              else
274                MINIRV32_HANDLE_MEM_STORE_CONTROL( addy, rs2 );
275            }
276            else
277            {
278              trap = (7+1); // Store access fault.
279              rval = addy;
280            }
281          }
282          else
283          {
284            switch( ( ir >> 12 ) & 0x7 )
285            {
286              //SB, SH, SW
287              case 0b000: MINIRV32_STORE1( addy, rs2 ); break;
288              case 0b001: MINIRV32_STORE2( addy, rs2 ); break;
289              case 0b010: MINIRV32_STORE4( addy, rs2 ); break;
290              default: trap = (2+1);
291            }
292          }
293          break;
294        }
295        case 0b0010011: // Op-immediate
296        case 0b0110011: // Op
297        {
298          uint32_t imm = ir >> 20;
299          imm = imm | (( imm & 0x800 )?0xfffff000:0);
300          uint32_t rs1 = REG((ir >> 15) & 0x1f);
301          uint32_t is_reg = !!( ir & 0b100000 );
302          uint32_t rs2 = is_reg ? REG(imm & 0x1f) : imm;
303
304          if( is_reg && ( ir & 0x02000000 ) )
305          {
306            switch( (ir>>12)&7 ) //0x02000000 = RV32M
307            {
308              case 0b000: rval = rs1 * rs2; break; // MUL
309              case 0b001: rval = ((int64_t)((int32_t)rs1) * (int64_t)((int32_t)rs2)) >> 32; break; // MULH
310              case 0b010: rval = ((int64_t)((int32_t)rs1) * (uint64_t)rs2) >> 32; break; // MULHSU
311              case 0b011: rval = ((uint64_t)rs1 * (uint64_t)rs2) >> 32; break; // MULHU
312              case 0b100: if( rs2 == 0 ) rval = -1; else rval = ((int32_t)rs1 == INT32_MIN && (int32_t)rs2 == -1) ? rs1 : ((int32_t)rs1 / (int32_t)rs2); break; // DIV
313              case 0b101: if( rs2 == 0 ) rval = 0xffffffff; else rval = rs1 / rs2; break; // DIVU
314              case 0b110: if( rs2 == 0 ) rval = rs1; else rval = ((int32_t)rs1 == INT32_MIN && (int32_t)rs2 == -1) ? 0 : ((uint32_t)((int32_t)rs1 % (int32_t)rs2)); break; // REM
315              case 0b111: if( rs2 == 0 ) rval = rs1; else rval = rs1 % rs2; break; // REMU
316            }
317          }
318          else
319          {
320            switch( (ir>>12)&7 ) // These could be either op-immediate or op commands.  Be careful.
321            {
322              case 0b000: rval = (is_reg && (ir & 0x40000000) ) ? ( rs1 - rs2 ) : ( rs1 + rs2 ); break; 
323              case 0b001: rval = rs1 << (rs2 & 0x1F); break;
324              case 0b010: rval = (int32_t)rs1 < (int32_t)rs2; break;
325              case 0b011: rval = rs1 < rs2; break;
326              case 0b100: rval = rs1 ^ rs2; break;
327              case 0b101: rval = (ir & 0x40000000 ) ? ( ((int32_t)rs1) >> (rs2 & 0x1F) ) : ( rs1 >> (rs2 & 0x1F) ); break;
328              case 0b110: rval = rs1 | rs2; break;
329              case 0b111: rval = rs1 & rs2; break;
330            }
331          }
332          break;
333        }
334        case 0b0001111:
335          rdid = 0;   // fencetype = (ir >> 12) & 0b111; We ignore fences in this impl.
336          break;
337        case 0b1110011: // Zifencei+Zicsr
338        {
339          uint32_t csrno = ir >> 20;
340          int microop = ( ir >> 12 ) & 0b111;
341          if( (microop & 3) ) // It's a Zicsr function.
342          {
343            int rs1imm = (ir >> 15) & 0x1f;
344            uint32_t rs1 = REG(rs1imm);
345            uint32_t writeval = rs1;
346
347            // https://raw.githubusercontent.com/riscv/virtual-memory/main/specs/663-Svpbmt.pdf
348            // Generally, support for Zicsr
349            switch( csrno )
350            {
351            case 0x340: rval = CSR( mscratch ); break;
352            case 0x305: rval = CSR( mtvec ); break;
353            case 0x304: rval = CSR( mie ); break;
354            case 0xC00: rval = cycle; break;
355            case 0x344: rval = CSR( mip ); break;
356            case 0x341: rval = CSR( mepc ); break;
357            case 0x300: rval = CSR( mstatus ); break; //mstatus
358            case 0x342: rval = CSR( mcause ); break;
359            case 0x343: rval = CSR( mtval ); break;
360            case 0xf11: rval = 0xff0ff0ff; break; //mvendorid
361            case 0x301: rval = 0x40401101; break; //misa (XLEN=32, IMA+X)
362            //case 0x3B0: rval = 0; break; //pmpaddr0
363            //case 0x3a0: rval = 0; break; //pmpcfg0
364            //case 0xf12: rval = 0x00000000; break; //marchid
365            //case 0xf13: rval = 0x00000000; break; //mimpid
366            //case 0xf14: rval = 0x00000000; break; //mhartid
367            default:
368              MINIRV32_OTHERCSR_READ( csrno, rval );
369              break;
370            }
371
372            switch( microop )
373            {
374              case 0b001: writeval = rs1; break;        //CSRRW
375              case 0b010: writeval = rval | rs1; break;    //CSRRS
376              case 0b011: writeval = rval & ~rs1; break;    //CSRRC
377              case 0b101: writeval = rs1imm; break;      //CSRRWI
378              case 0b110: writeval = rval | rs1imm; break;  //CSRRSI
379              case 0b111: writeval = rval & ~rs1imm; break;  //CSRRCI
380            }
381
382            switch( csrno )
383            {
384            case 0x340: SETCSR( mscratch, writeval ); break;
385            case 0x305: SETCSR( mtvec, writeval ); break;
386            case 0x304: SETCSR( mie, writeval ); break;
387            case 0x344: SETCSR( mip, writeval ); break;
388            case 0x341: SETCSR( mepc, writeval ); break;
389            case 0x300: SETCSR( mstatus, writeval ); break; //mstatus
390            case 0x342: SETCSR( mcause, writeval ); break;
391            case 0x343: SETCSR( mtval, writeval ); break;
392            //case 0x3a0: break; //pmpcfg0
393            //case 0x3B0: break; //pmpaddr0
394            //case 0xf11: break; //mvendorid
395            //case 0xf12: break; //marchid
396            //case 0xf13: break; //mimpid
397            //case 0xf14: break; //mhartid
398            //case 0x301: break; //misa
399            default:
400              MINIRV32_OTHERCSR_WRITE( csrno, writeval );
401              break;
402            }
403          }
404          else if( microop == 0b000 ) // "SYSTEM"
405          {
406            rdid = 0;
407            if( csrno == 0x105 ) //WFI (Wait for interrupts)
408            {
409              CSR( mstatus ) |= 8;    //Enable interrupts
410              CSR( extraflags ) |= 4; //Infor environment we want to go to sleep.
411              SETCSR( pc, pc + 4 );
412              return 1;
413            }
414            else if( ( ( csrno & 0xff ) == 0x02 ) )  // MRET
415            {
416              //https://raw.githubusercontent.com/riscv/virtual-memory/main/specs/663-Svpbmt.pdf
417              //Table 7.6. MRET then in mstatus/mstatush sets MPV=0, MPP=0, MIE=MPIE, and MPIE=1. La
418              // Should also update mstatus to reflect correct mode.
419              uint32_t startmstatus = CSR( mstatus );
420              uint32_t startextraflags = CSR( extraflags );
421              SETCSR( mstatus , (( startmstatus & 0x80) >> 4) | ((startextraflags&3) << 11) | 0x80 );
422              SETCSR( extraflags, (startextraflags & ~3) | ((startmstatus >> 11) & 3) );
423              pc = CSR( mepc ) -4;
424            }
425            else
426            {
427              switch( csrno )
428              {
429              case 0: trap = ( CSR( extraflags ) & 3) ? (11+1) : (8+1); break; // ECALL; 8 = "Environment call from U-mode"; 11 = "Environment call from M-mode"
430              case 1:  trap = (3+1); break; // EBREAK 3 = "Breakpoint"
431              default: trap = (2+1); break; // Illegal opcode.
432              }
433            }
434          }
435          else
436            trap = (2+1);         // Note micrrop 0b100 == undefined.
437          break;
438        }
439        case 0b0101111: // RV32A
440        {
441          uint32_t rs1 = REG((ir >> 15) & 0x1f);
442          uint32_t rs2 = REG((ir >> 20) & 0x1f);
443          uint32_t irmid = ( ir>>27 ) & 0x1f;
444
445          rs1 -= MINIRV32_RAM_IMAGE_OFFSET;
446
447          // We don't implement load/store from UART or CLNT with RV32A here.
448
449          if( rs1 >= MINI_RV32_RAM_SIZE-3 )
450          {
451            trap = (7+1); //Store/AMO access fault
452            rval = rs1 + MINIRV32_RAM_IMAGE_OFFSET;
453          }
454          else
455          {
456            rval = MINIRV32_LOAD4( rs1 );
457
458            // Referenced a little bit of https://github.com/franzflasch/riscv_em/blob/master/src/core/core.c
459            uint32_t dowrite = 1;
460            switch( irmid )
461            {
462              case 0b00010: //LR.W
463                dowrite = 0;
464                CSR( extraflags ) = (CSR( extraflags ) & 0b111) | (rs1<<3);
465                break;
466              case 0b00011:  //SC.W (Make sure we have a slot, and, it's valid)
467                rval = ( CSR( extraflags ) >> 3 != ( rs1 & 0x1fffffff ) );  // Validate that our reservation slot is OK.
468                dowrite = !rval; // Only write if slot is valid.
469                break;
470              case 0b00001: break; //AMOSWAP.W
471              case 0b00000: rs2 += rval; break; //AMOADD.W
472              case 0b00100: rs2 ^= rval; break; //AMOXOR.W
473              case 0b01100: rs2 &= rval; break; //AMOAND.W
474              case 0b01000: rs2 |= rval; break; //AMOOR.W
475              case 0b10000: rs2 = ((int32_t)rs2<(int32_t)rval)?rs2:rval; break; //AMOMIN.W
476              case 0b10100: rs2 = ((int32_t)rs2>(int32_t)rval)?rs2:rval; break; //AMOMAX.W
477              case 0b11000: rs2 = (rs2<rval)?rs2:rval; break; //AMOMINU.W
478              case 0b11100: rs2 = (rs2>rval)?rs2:rval; break; //AMOMAXU.W
479              default: trap = (2+1); dowrite = 0; break; //Not supported.
480            }
481            if( dowrite ) MINIRV32_STORE4( rs1, rs2 );
482          }
483          break;
484        }
485        default: trap = (2+1); // Fault: Invalid opcode.
486      }
487
488      // If there was a trap, do NOT allow register writeback.
489      if( trap )
490        break;
491
492      if( rdid )
493      {
494        REGSET( rdid, rval ); // Write back register.
495      }
496    }
497
498    MINIRV32_POSTEXEC( pc, ir, trap );
499
500    pc += 4;
501  }
502
503  // Handle traps and interrupts.
504  if( trap )
505  {
506    if( trap & 0x80000000 ) // If prefixed with 1 in MSB, it's an interrupt, not a trap.
507    {
508      SETCSR( mcause, trap );
509      SETCSR( mtval, 0 );
510      pc += 4; // PC needs to point to where the PC will return to.
511    }
512    else
513    {
514      SETCSR( mcause,  trap - 1 );
515      SETCSR( mtval, (trap > 5 && trap <= 8)? rval : pc );
516    }
517    SETCSR( mepc, pc ); //TRICKY: The kernel advances mepc automatically.
518    //CSR( mstatus ) & 8 = MIE, & 0x80 = MPIE
519    // On an interrupt, the system moves current MIE into MPIE
520    SETCSR( mstatus, (( CSR( mstatus ) & 0x08) << 4) | (( CSR( extraflags ) & 3 ) << 11) );
521    pc = (CSR( mtvec ) - 4);
522
523    // If trapping, always enter machine mode.
524    CSR( extraflags ) |= 3;
525
526    trap = 0;
527    pc += 4;
528  }
529
530  if( CSR( cyclel ) > cycle ) CSR( cycleh )++;
531  SETCSR( cyclel, cycle );
532  SETCSR( pc, pc );
533  return 0;
534}
535
536#endif
537
538#endif
14. 多处理器系统与中断机制¶

Take-away Messages¶

课后习题/编程作业¶

1. 调试 Thread-OS¶

2. 编程实践¶
